With the rapid development of the integrated circuit manufacturing industry, the requirements for integrated circuit packaging technologies are also increasing. Existing packaging technologies include ball grid array packaging (BGA), chip scale packaging (CSP), wafer level packaging (WLP), three-dimensional packaging (3D), and system packaging (SiP) and so on. Among them, the wafer level packaging (WLP) is gradually adopted by most semiconductor manufacturers due to its excellent advantages, all or most of its process steps are completed on a silicon wafer when the pre-process has been completed, and finally the wafer is directly cut into separate devices. Wafer level packaging (WLP) has its unique advantages: {circle around (1)} package processing efficiency is high because multiple wafers can be processed at the same time; {circle around (2)} the advantages of flip-chip packaging, i.e., being light, thin, short and small, are achieved; {circle around (3)} in comparison with the pre-process, only two processes, i.e., making redistribution layers (RDL) of pins and fabricating bumps, are added, and the rest of the WLP are all natural processes; and {circle around (4)} the multiple tests in the traditional packaging are reduced. Therefore, the world's major IC packaging companies have invested in the research, development and production of such WLP. The current disadvantages of WLP lie in low pin count, no standardization and high cost. In addition to technologies required for the pre-process, such as metal deposition, photolithography and etching, the key technologies involved in WLP further include RDL technology and bump fabrication technology. In general, the on-chip terminal pads are square aluminum layers routed to the periphery of the die. To accommodate WLP for a wider pad pitch of SMT two-stage packaging, these pads need to be redistributed so that these pads are arranged into an array on the active surface of the chip, rather than being arranged at the periphery of the chip, which requires the redistribution layer (RDL) technology.
A redistribution layer (RDL) is an interface between a chip and a package in a flip-chip assembly. The redistribution layer is an additional metal layer that consists of a core metal top wiring and is used to bind the I/O pads of a bare chip outward to other locations such as bump pads. The bumps are usually arranged in a grid pattern, with each bump having two bonding pads (one being on the top, and one being on the bottom) that are respectively connected to a redistribution layer and a package substrate.
In the existing fan-out chip packaging technology, a semiconductor chip is usually pasted directly onto a film, and then the semiconductor chip is transferred to a supporting substrate or another support part. After the semiconductor chip is transferred, the film needs to be removed. However, adhesive residue on the film tends to remain on the surface of the semiconductor chip when the film is removed, which may contaminate the semiconductor chip.
In order to overcome the above defects, one existing solution is: first fabricating a redistribution layer directly on the surface of a silicon supporting substrate, and then fabricating welding bumps on the surface of a semiconductor chip, aligning the semiconductor chip to the silicon supporting substrate and packaging the semiconductor chip on the surface of the silicon supporting substrate, and finally reducing the thickness of the silicon supporting substrate. The advantage of this process is that the semiconductor chip can be prevented from being contaminated by the adhesive of the film. However, since the redistribution layer is fabricated on a silicon supporting substrate, the packaging of the semiconductor chip requires very high alignment accuracy to ensure the electrical property, and thus it is difficult to realize this process, and rate of finished products may decrease easily.
In view of the above, it is necessary to provide a wafer level chip packaging method that can effectively prevent the contamination of semiconductor chips.